1. Field of the Invention
The present invention relates to memories (e.g., NAND- or NOR-type flash memories) and, more particularly, to embedded error correction codes (ECC) within such memories.
2. Description of the Related Art
In the last few years, semiconductor memories have been produced with very high storage capacities. Such increases in storage capacity have been achieved by using multi-level storage. The multi-level storage allows many bits of information to be stored within an individual memory cell, where before only a single bit could be stored.
It is moreover known that in order to read a two-level memory cell (storing 1 bit) an appropriate electric quantity linked to the state of the cell is compared with a reference value, and, according to the outcome of the comparison, it may be determined whether the memory cell contains a logic “0” or a logic “1”.
In the case of cells that are able to store r bits, reading is carried out by comparing the electric quantity of the cell with 2r−1 reference levels. The outcome of the comparisons allows for reconstruction of the binary information contained in the cell.
The multilevel approach can be applied both to volatile memories (such as DRAM memories) and to nonvolatile memories (such as EEPROM and Flash memories). In either case, the increase in the number of bits per cell renders more critical the tolerance to disturbance, the retention of the information and the accuracy of the operations of reading and writing. Unfortunately, incremental increases in storage capacity tends to reduce the reliability. For these reasons it is believed that the use of error correcting codes (ECC) will be fundamental above all for high capacity multilevel memories.
At present, commercially available memory devices with larger capacities contain some hundreds of millions of bits, and in the next few years it is forecast that such memory devices will have even greater capacity. This increase in the number of cells tends to reduce the mean time to failure (MTTF) of the entire memory device. However, given the need to create increasingly reliable equipment or systems, the level of reliability required for the individual memory component becomes increasingly stringent. However, errors in a memory chip cannot be eliminated completely and, generally, less errors in a memory require a reduction in performance or an increase in costs.
A very effective way to increase reliability is represented by the design of memories immune from error using ECC, which are codes that are able to detect and correct errors in the memory data. In particular, codes with correction of a single error, or detection of a double error and correction of single error, are used in semiconductor memory devices of various types. In this connection, see, for example, K. Furutani, K. Arimoto, H. Miyamoto, T. Kobayashi, K.-I. Yasuda, and K. Mashiko, “A Built-in Hamming Code ECC Circuit for DRAM's”, IEEE J. Solid-State Circuits, Vol. 24, No. 1, February 1989, pp. 50-56, and T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takeuchi, K. Ohuchi, “A Compact On-Chip ECC For Low-Cost Flash Memories”, IEEE J. Solid-State Circuits, Vol. 32, No. 5, May 1997, pp. 662-669.
The errors in the memories are normally classified as “soft” errors and “hard” errors. “Soft” errors are a random, non-repetitive and non-permanent change in the state of a cell. “Soft” errors are caused by occasional electrical noise or are induced by radiation (a particles, cosmic rays, etc.) that affects a very limited number of cells at a time, and may be recovered in the next writing cycle. “Hard” errors are, instead, a permanent physical failure because of a fault present in the device. In practice, “hard” errors are much less frequent than “soft” errors.
ECCs enable drastic reduction in the effects of “soft” errors, which represent the more serious problem of the two, especially for multilevel memories. ECCs can moreover prove useful for the purpose of recovering some “hard” errors.
To protect the information stored in the memory using ECCs, it is necessary to add to each stored word a certain number of control bits appropriately calculated. The operation that associates to each stored word a precise value of the control bits is called encoding. The control bits calculated by the circuit that carries out encoding are stored together with the information word. Each word stored will be subsequently read together with the control bits that pertain to it. The decoding circuit is able to detect and correct a certain number of erroneous bits per word by appropriately comparing the value of the control bits with the value of the information bits.
The number of control bits necessary to add to each stored word is determined according to the length of the word itself and the number of errors per word that are desired to be corrected. Generally, error-correction encoding can be extended from the binary alphabet (containing only the two symbols “0” and “1”) to an alphabet containing q symbols. In this case, encoding consists in the addition of a certain number of symbols (no longer of bits) to each word to be stored, and the correction of the errors includes the correction of the erroneous symbols.
Generally, the ECCs are managed outside of the memory by an external controller. For example, an external controller calculates an ECC associated with data and then stores the data with the ECC in the memory. When the external controller reads the data, it also reads the stored ECC. The external controller then performs the ECC check and possibly an error correction, if necessary. The burden on the external controller is great as the external controller must take care of ECC generation, checking, and tracking where in memory the ECCs are stored. However, the external controller does have complete control as to whether or not an ECC check is performed and the type of ECC check performed.
U.S. Patent application number U.S. 2004/0083334 A1 to Chang et al. describes a system wherein an ECC generator is incorporated within the memory, and allows for ECC calculation of subpages. However, there is no control provided to an external user whether or not an ECC will be performed and there is no control as to the type of ECC generated.
Thus, it is desirable to provide more flexibility and control regarding error correction through ECC for a user of a memory.